NXP Semiconductors /MIMXRT1062 /SNVS /HPLR

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Interpret as HPLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ZMK_WSL_0)ZMK_WSL 0 (ZMK_RSL_0)ZMK_RSL 0 (SRTC_SL_0)SRTC_SL 0 (LPCALB_SL_0)LPCALB_SL 0 (MC_SL_0)MC_SL 0 (GPR_SL_0)GPR_SL 0 (LPSVCR_SL_0)LPSVCR_SL 0 (LPTDCR_SL_0)LPTDCR_SL 0 (MKS_SL_0)MKS_SL 0 (HPSVCR_L_0)HPSVCR_L 0 (HPSICR_L_0)HPSICR_L 0 (HAC_L_0)HAC_L

ZMK_WSL=ZMK_WSL_0, MKS_SL=MKS_SL_0, LPSVCR_SL=LPSVCR_SL_0, MC_SL=MC_SL_0, HPSICR_L=HPSICR_L_0, HPSVCR_L=HPSVCR_L_0, LPCALB_SL=LPCALB_SL_0, SRTC_SL=SRTC_SL_0, GPR_SL=GPR_SL_0, HAC_L=HAC_L_0, LPTDCR_SL=LPTDCR_SL_0, ZMK_RSL=ZMK_RSL_0

Description

SNVS_HP Lock Register

Fields

ZMK_WSL

Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR

0 (ZMK_WSL_0): Write access is allowed

1 (ZMK_WSL_1): Write access is not allowed

ZMK_RSL

Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR

0 (ZMK_RSL_0): Read access is allowed (only in software Programming mode)

1 (ZMK_RSL_1): Read access is not allowed

SRTC_SL

Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits

0 (SRTC_SL_0): Write access is allowed

1 (SRTC_SL_1): Write access is not allowed

LPCALB_SL

LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)

0 (LPCALB_SL_0): Write access is allowed

1 (LPCALB_SL_1): Write access is not allowed

MC_SL

Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit

0 (MC_SL_0): Write access (increment) is allowed

1 (MC_SL_1): Write access (increment) is not allowed

GPR_SL

General Purpose Register Soft Lock When set, prevents any writes to the GPR

0 (GPR_SL_0): Write access is allowed

1 (GPR_SL_1): Write access is not allowed

LPSVCR_SL

LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR

0 (LPSVCR_SL_0): Write access is allowed

1 (LPSVCR_SL_1): Write access is not allowed

LPTDCR_SL

LP Tamper Detectors Configuration Register Soft Lock When set, prevents any writes to the LPTDCR

0 (LPTDCR_SL_0): Write access is allowed

1 (LPTDCR_SL_1): Write access is not allowed

MKS_SL

Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR

0 (MKS_SL_0): Write access is allowed

1 (MKS_SL_1): Write access is not allowed

HPSVCR_L

HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR

0 (HPSVCR_L_0): Write access is allowed

1 (HPSVCR_L_1): Write access is not allowed

HPSICR_L

HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR

0 (HPSICR_L_0): Write access is allowed

1 (HPSICR_L_1): Write access is not allowed

HAC_L

High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR

0 (HAC_L_0): Write access is allowed

1 (HAC_L_1): Write access is not allowed

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